Guard rings are structures fabricated along the perimeter of an integrated circuit chip to prevent delamination of the various layers of the integrated circuit chip and other edge damage that may occur during “dicing” of individual integrated circuit chips. The guard rings can protect the active area of the chip from moisture, mobile ions, and mechanical damage. For example, the guard rings can prevent moisture from corroding the structures on the integrated circuit chip. Also, the guard rings can prevent damage to the components within an active area of the integrated circuit due to cracking that may form during the dicing process.
More specifically, after formation of the active and passive components, the wafer is cut or diced into individual integrated circuit chips, either by sawing or by scribing and breaking. During the cutting or dicing process, the wafer is subjected to high shear stresses which can cause cracks extending inwardly from the edges of each chip. Due to the stresses encountered when dicing the chip, or even later during use, cracks can propagate inward from the edges of the chip and eventually reach the active portion of the chip, damaging semiconductor devices disposed in the active region. Guard rings, though, can prevent the propagation of cracks from reaching the active region of the chip.
High speed interconnects are required in computer systems, at the chip level, for chip-to-chip communications and for server-to-server communications. As device speeds increase, it is increasingly difficult for electrical interconnects to provide the required performance in terms of bandwidth, power consumption, and cross-talk. For this reason, optical interconnects have been implemented, which provide an attractive alternative to the electrical connections. However, the cost of optical interconnects is high, and must be reduced in order for optical interconnects to be competitive in the marketplace.
Optical interconnects require Si waveguide structures integrated onto a CMOS die (chip). The Si waveguide structure, though, is not compatible with a standard edge seal ring, e.g., guard ring, which is a wall of metal that surrounds the chip (die). For example, guard rings are typically in the form of a metallic ring-like structure positioned between the active region of the chip and the edge of the chip so as to encompass the active region of the chip. The guard ring typically extends vertically upward from a semiconductor device layer of the chip through all of the back-end-of-line (“BEOL”) metallization layers (also referred to herein as wiring levels) of the chip. For example, guard rings are typically formed by a plurality of metal vias and wiring layers that surround other circuitry of the chip. These metal vias and wiring layers are typically formed by depositing metal layers within openings of a dielectric layer. However, by using a standard guard ring, the light into or out of the waveguide structure will be blocked at the perimeter of the chip.